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ADC10065 10-Bit 65 MSPS 3V A/D Converter
August 2003
ADC10065 10-Bit 65 MSPS 3V A/D Converter
General Description
The ADC10065 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 68.4 mW at 65 MSPS, including the reference current. The Standby feature reduces power consumption to just 14 .1 mW. The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is 10-bit offset binary, or two's complement. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of -40C to +85C.
Features
n Single +3.0V operation n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing n 400 MHz -3 dB input bandwidth n Low power consumption n Standby mode n On-chip reference and sample-and-hold amplifier n Offset binary or two's complement data format n Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families n 28-pin TSSOP package
Key Specifications
n n n n n n n n n Resolution Conversion Rate Full Power Bandwidth DNL SNR (fIN = 11 MHz) SFDR (fIN = 11 MHz) Data Latency Supply Voltage Power Consumption, 65 MHz 10 Bits 65 MSPS 400 MHz 0.3 LSB (typ) 59.6 dB (typ) -80 dB (typ) 6 Clock Cycles +3.0V 68.4 mW
Applications
n n n n n n n n Ultrasound and Imaging Instrumentation Cellular Based Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends
Connection Diagram
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(c) 2003 National Semiconductor Corporation
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ADC10065
Ordering Information
Industrial (-40C TA +85C) ADC10065CIMT ADC10065CIMTX NS Package 28 Pin TSSOP 28 Pin TSSOP Tape & Reel
Block Diagram
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ADC10065
Pin Descriptions and Equivalent Circuits
Pin No. ANALOG I/O Inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P. This pin may be tied to VCOM for single-ended operation. Symbol Equivalent Circuit Description
12
VIN-
13
VIN+
Non-inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P.
6
VREF
Reference input. This pin should be bypassed to VSSA with a 1 F monolithic capacitor. VREF is 1.20V nominal. This pin may be driven by a 1.20V external reference if desired.
7
VREFT
4
VCOM
VREFT and VREFB are high impedance reference bypass pins only. Connect a 1 F capacitor from each of these pins to VSSA. VCOM should also be bypassed with a 1 F capacitor to VSSA. VCOM may be used to set the input common voltage VCM.
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VREFB
DIGITAL I/O 1 CLK Digital clock input. The range of frequencies for this input is 10 MHz to 65 MHz. The input is sampled on the rising edge of this input. DF = "1" Two's Complement DF = "0" Offset Binary This is the standby pin. When high, this pin sets the converter into standby mode. When this pin is low, the converter is in active mode. IRS = "VDDA" 2.0 VP-P input range IRS = "VSSA" 1.5 VP-P input range IRS = "Floating" 1.0 VP-P input range
15
DF
28
STBY
5
IRS (Input Range Select)
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ADC10065
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit
(Continued) Description
16-20, 23-27
D0-D9
Digital output data. D0 is the LSB and D9 is the MSB of the binary output word.
ANALOG POWER Positive analog supply pins. These pins should be connected to a quiet 3.0V source and bypassed to analog ground with a 0.1 F monolithic capacitor located within 1 cm of these pins. A 4.7 F capacitor should also be used in parallel. Ground return for the analog supply. Positive digital supply pins for the ADC10065's output drivers. This pin should be bypassed to digital ground with a 0.1 F monolithic capacitor located within 1 cm of this pin. A 4.7 F capacitor should also be used in parallel. The voltage on this pin should never exceed the voltage on VDDA by more than 300 mV. The ground return for the digital supply for the output drivers. This pin should be connected to the digital ground, but not near the analog ground.
2, 9, 10
VDDA
3, 11, 14 DIGITAL POWER
VSSA
22
VDDIO
21
VSSIO
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ADC10065
Absolute Maximum Ratings
2)
(Notes 1,
Operating Ratings
Operating Temperature Range VDDA (Supply Voltage) VDDIO (Output Driver Supply Voltage) VREF |VSSA-VSSIO| -40C TA +85C +2.7V to +3.6V +2.5V to VDDA 1.20V 100 mV
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDDA, VDDIO Voltage on Any Pin to GND Input Current on Any Pin Package Input Current (Note 3) Package Dissipation at T = 25C ESD Susceptibility Human Body Model (Note 5) Machine Model (Note 5) Soldering Temperature Infrared, 10 sec. (Note 6) Storage Temperature 2500V 250V 235C -65C to +150C 3.9V -0.3V to VDDA or VDDIO +0.3V
25 mA 50 mA
See (Note 4)
NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (External Supply) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25C. Symbol Parameter No Missing Codes Guaranteed INL DNL GE OE Integral Non-Linearity (Note 11) Differential Non-Linearity Gain Error Offset Error (VIN+ = VIN-) Under Range Output Code Over Range Output Code FPBW VCM VREF VREFTC Full Power Bandwidth Common Mode Input Voltage Reference Voltage Reference Voltage Temperature Coefficient STBY = 1 STBY = 0 STBY = 1, fIN = 0 Hz STBY = 0, fIN = 0 Hz STBY = 1 STBY = 0 0.5 1.2 REFERENCE AND INPUT CHARACTERISTICS 1.5 V V ppm/C FIN = 500 kHz, -0 dB Full Scale FIN = 500 kHz, -0 dB Full Scale Positive Error Negative Error Conditions Min 10 -1.0 -0.9 -1.5 -1.5 -1.4 Typ Max Units Bits STATIC CONVERTER CHARACTERISTICS
0.3 0.3
+0.4 +0.03 0.2 0 1023 400
+1.1 +0.9 +1.9 +1.9 +1.7
LSB LSB % FS % FS % FS
MHz
80
POWER SUPPLY CHARACTERISTICS IVDDA IVDDIO PWR Analog Supply Current Digital Supply Current Power Consumption 4.7 22 0 0.97 14.1 68.4 1.2 18.0 90 6.0 29 mA mA mA mA mW mW
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ADC10065
DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25C
Symbol CLK, DF, STBY, SENSE Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current D0-D9 OUTPUT CHARACTERISTICS Logical "1" Output Voltage Logical "0" Output Voltage DYNAMIC CONVERTER CHARACTERISTICS ENOB SNR SINAD Effective Number of Bits Signal-to-Noise Ratio Signal-to-Noise Ratio + Distortion fIN = 11 MHz fIN = 32 MHz fIN = 11 MHz fIN = 32 MHz fIN = 11 MHz fIN = 32 MHz fIN = 11 MHz 2nd HD 2nd Harmonic fIN = 32 MHz fIN = 11 MHz 3rd HD 3rd Harmonic fIN = 32 MHz 9.4, 9.3 9.3, 9.2 58.6, 58 58.5, 57.9 58.3, 57.6 58, 57.4 -75.6, -69.7 -72.7, -68.9 -66.2, -63 -65.4, -63.3 -66.2, -63 -65.4, -63.3 -75.8, -74.5 -74.4, -73.3 9.6 9.5 59.6 59.3 59.4 59 -90 -82 -74 -72 -74 -72 -80 -80 Bits Bits dB dB dB dB dBc dBc dBc dBc dB dB dBc dBc IOUT = -0.5 mA IOUT = 1.6 mA VDDIO-0.2 0.4 V V -10 2 0.8 +10 V V A A Parameter Conditions Min Typ Max Units
THD
Total Harmonic Distortion (First 6 Harmonics)
fIN = 11 MHz fIN = 32 MHz fIN = 11 MHz fIN = 32 MHz
SFDR
Spurious Free Dynamic Range (Excluding 2nd and 3rd Harmonic)
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ADC10065
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25C Symbol Parameter Conditions Min (Note 11) Typ (Note 11) Max (Note 11) 65 7.69 7.69 6 T = 25C 2 1 1 2 Differential VIN step from 3V to 0V to get accurate conversion 1 20 3.4 5 6 Units
CLK, DF, STBY, SENSE fCLK tCH tCL tCONV tOD tAD tAJ Maximum Clock Frequency Clock High Time Clock Low Time Conversion Latency Data Output Delay after a Rising Clock Edge Aperture Delay Aperture Jitter Over Range Recovery Time tSTBY Standby Mode Exit Cycle MHz (min) ns ns Cycles ns ns ns ps (RMS) Clock Cycle Cycles
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = VSSA = VSSIO = 0V, unless otherwise specified. Note 3: When the voltage at any pin exceeds the power supplies (VIN < VSSA or VIN > VDDA, VDDIO), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA)/JA. In the 28-pin TSSOP, JA is 96C/W, so PDMAX = 1,302 mW at 25C and 677 mW at the maximum operating ambient temperature of 85C. Note that the power dissipation of this device under normal operation will typically be about 68.6 mW. The values for maximum power dissipation listed above will be reached only when the ADC10065 is operated in a severe fault condition. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through 0. Note 6: The 235C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top of the package body above 183C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220C. Only one excursion above 183C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be generated if the input goes above VDDA or VDDIO and below VSSA or VSSIO.
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Note 7: To guarantee accuracy, it is required that |VDDA-VDDIO| 100 mV and separate bypass capacitors are used at each power supply pin. Note 8: With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. Note 9: Typical figures are at TA = TJ = 25C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 10: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 11: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge. Note 12: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V. Note 13: IDDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR x (C0 x f0 + C1 x f1 + C2 + f2 +....C11 x f11) where VDR is the output driver supply voltage, Cn is the total load capacitance on the output pin, and fn is the average frequency at which the pin is toggling. Note 14: Power consumption includes output driver power. (fIN = 0 MHz). Note 15: The input bandwidth is limited using a 10 pF capacitor between VIN- and VIN+.
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ADC10065
Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error - Offset Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (12 LSB below the first code transition) through positive full scale (12 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC10065 is guaranteed not to have any missing codes. NEGATIVE FULL SCALE ERROR is the difference between the input voltage (VIN+ - VIN-) just causing a transition from negative full scale to the first code and its ideal value of 0.5 LSB. OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 112 LSB below positive full scale. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as:
where f1 is the RMS power of the fundamental (output) frequency and f2 through f6 are the RMS power in the first 6 harmonic frequencies. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output.
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ADC10065
Timing Diagram
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FIGURE 1. Clock and Data Timing Diagram
Transfer Characteristics
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FIGURE 2. Input vs. Output Transfer Characteristic
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ADC10065
Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle.
DNL DNL vs. fCLK
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DNL vs. Clock Duty Cycle (DC input)
DNL vs. Temperature
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INL
INL vs. fCLK
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ADC10065
Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued)
INL vs. Clock Duty Cycle SNR vs. VDDIO
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SNR vs. VDDA
SNR vs. fCLK
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INL vs. Temperature
SNR vs. Clock Duty Cycle
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ADC10065
Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued)
SNR vs. Temperature THD vs. VDDA
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THD vs. VDDIO
THD vs. fCLK
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SNR vs. IRS
THD vs. IRS
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ADC10065
Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued)
SINAD vs. VDDA SINAD vs. VDDIO
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THD vs. Clock Duty Cycle
SINAD vs. Clock Duty Cycle
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THD vs. Temperature
SINAD vs. Temperature
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ADC10065
Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued)
SINAD vs. fCLK SFDR vs. VDDIO
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SINAD vs. IRS
SFDR vs. fCLK
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SFDR vs. VDDA
SFDR vs. IRS
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ADC10065
Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued)
SFDR vs. Clock Duty Cycle Spectral Response @ 11 MHz Input
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SFDR vs. Temperature
Spectral Response @ 32 MHz Input
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Power Consumption vs. fCLK
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ADC10065
Functional Description
The ADC10065 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. Each analog input signal should have a peak-to-peak voltage equal to 2.0V, 1.5V or 1.0V, depending on the state of the IRS pin (pin 5), be centered around VCM/2 and be 180 out of phase with each other.
Applications Information
1.0 ANALOG INPUTS The ADC10065 has two analog signal inputs, VIN+ and VIN-. These two pins form a differential input pair. There is one common mode pin VCM that may be used to set the common mode input voltage. 1.1 REFERENCE PINS The ADC10065 is designed to operate with a 1.2V reference, but performs well with reference voltages in the range of 0.8V to 2.0V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC10065. It is very important that all grounds associated with the reference voltage and the input signal make connection to the analog ground plane at a single point to minimize the effects of noise currents in the ground path. The three Reference Bypass Pins VREF, VREFT and VREFB, are made available for bypass purposes only. These pins should each be bypassed to ground with a 0.1 F capacitor. DO NOT LOAD these pins. 1.2 SIGNAL INPUTS The signal inputs are VIN+ and VIN-. The input signal amplitude is defined as VIN+ - VIN- and is represented schematically in Figure 3:
The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal. To prevent this, use 18 series resistors at each of the signal inputs with a 10 pF capacitor across the inputs, as can be seen in Figure 5. These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The 10 pF capacitor value is for undersampling application and should be replaced with a 68 pF capacitor for Nyquist application. 1.3 CLK PIN The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 10 MHz to 65 MHz with rise and fall times of less than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the lowest sample rate to 10 MSPS. The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC10065 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range of 40% to 60%. 1.4 STBY PIN The STBY pin, when high, holds the ADC10065 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 15 mW. The output data pins are undefined in this mode. Power consumption during power-down is not affected by the clock frequency, or by whether there is a clock signal present. The data in the pipeline is corrupted while in the power down. 1.5 DF PIN The DF pin, when high, forces the ADC10065 to output the 2's complement data format. When DF is tied low, the output format is offset binary. 1.6 IRS PIN The IRS (Input Range Select) pin defines the input signal amplitude that will produce a full scale output. The table below describes the function of the IRS pin. TABLE 1. IRS Pin Functions IRS Pin VDDA VSSA Floating Full-Scale Input 2.0VP-P 1.5VP-P 1.0VP-P
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FIGURE 3. Input Voltage Waveforms for a 2VP-P Input A single ended input signal is shown in Figure 4.
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FIGURE 4. Input Voltage Waveform for a 2VP-P Single Ended Input
1.7 OUTPUT PINS The ADC10065 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these outputs while the DF and STBY pins are low. While the tOD time provides information about output timing, a simple way to capture a valid output is to latch the data on the rising edge of the conversion clock. Be very careful when driving a high capacitance bus. The more capacitance the output drivers
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ADC10065
Applications Information
(Continued)
must charge for each conversion, the more instantaneous digital current flows through VDDIO and VSSIO. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load currents at
the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry. Only one driven input should be ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. 1.8 APPLICATION SCHEMATICS The following figures show simple examples of using the ADC10065. Figure 5 shows a typical differentially driven input. Figure 6 shows a single ended application circuit.
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FIGURE 5. A Simple Application Using a Differential Driving Source
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FIGURE 6. A Simple Application Using a Single Ended Driving Source
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ADC10065 10-Bit 65 MSPS 3V A/D Converter
Physical Dimensions
inches (millimeters) unless otherwise noted
28-Lead TSSOP Package Ordering Number ADC10065CIMT NS Package Number MTC28
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